| 摘要 |
PURPOSE: To use the logic circuit of a low speed by receiving data bits from a bit shifter means, storing the data bits in a received order and supplying parallel output words packed in an (n)-bit width by the occurrence of MSB control signals. CONSTITUTION: When a most significant bit(MSB) is supplied to a line 34, a bit shifter 30 also supplies shifted bits up to seven pieces from the MSB position through seven parallel lines 46 and an OR gate 60 to a 7-bit parallel intermediate register 48 simultaneously. Data are stored by feeding them back from the output through the line 52, an AND gate 58 and the OR gate 60 to the input in the order of being received in the intermediate register 48. Then, the parallel output words packed by the (n)-bit width are supplied by the occurrence of the MSB control signals. Thus, the logic circuit of the low speed is made usable. |
