发明名称
摘要 PURPOSE:To perform pulse train recording which can be formed into an one- chip IC with a simple circuit configuration, by successively controlling plural switching circuits in accordance with serial data, in which data to be added to each head are successively arranged, and making an electric current of a direction corresponding to data flow successively to each head for a prescribed period. CONSTITUTION:Clocks phi1 and phi2 and a pulse width setting pulse Ps are added to each terminal 4, 5, and 6 and data D0 are added to a terminal 7. The data d0 are serial data, in which data to be successively recorded by heads 11-14 are successively arranged and synchronized to the clock phi1. The cycle of the clock phi2 represents the one cycle of the serial data D0 and is added in a rate of one piece to four pieces of the clock phi1. The pulse Ps is to determine the pulse width of a pulse current +I or -I to be made to flow to each head and synchronized to the clock phi1. It is possible to make to flow a pulse-like current +I or -I of positive or negative polarity shown by g-t of the diagram to each head 11-14 in accordance with the ''H'' and ''L'' of the data D0.
申请公布号 JPH0361241(B2) 申请公布日期 1991.09.19
申请号 JP19820210915 申请日期 1982.12.01
申请人 SONY CORP 发明人 SEKO SATORU;SUGITA JUNKICHI
分类号 G11B5/09 主分类号 G11B5/09
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