| 摘要 |
PURPOSE:To respond to the change of linear velocity with simplified and inexpensive circuit configuration by frequency-dividing the oscilation output of a VCO with a frequency division ratio corresponding to designated linear velocity, outputting it as a reproducing clock, and varying the gain of a variable gain amplifier corresponding to the designated linear velocity. CONSTITUTION:Digital information data is recorded on a disk 1 by, for example, an EFM(Eight to Fourteen Modulation) system. A phase comparator 14 which compares the phase of an EFM signal of square pulse with that of the reproducing clock is provided at this PLL circuit 10 for clock generation, and the low- pass component of comparison output is passed through a low-pass filter 15, and goes to a phase error signal. The phase error signal is amplified with the variable gain amplifier 16, and goes to the control voltage of the VCO 17. A clock outputted from the VCO 17 is outputted as the reproducing clock in which it is 1/8-, 1/4-, and 1/2-frequency divided for the linear velocity with 1/2-frequency dividers 18-20 connected in series in three stages. In such a way, it is possible to respond to the change of the designated linear velocity with a single VCO. |
