发明名称 SEMICONDUCTOR MEMORY ARRAY
摘要 PURPOSE: To relieve the layout of a memory array and to facilitate its producing process by connecting bit line pairs on odd numbers to sense amplifier groups on odd numbers and connecting bit line pairs on even numbers to sense amplifier groups on even numbers among bit line pairs. CONSTITUTION: Many number of groups are formed with sense amplifiers, and one sense amplifier is connected to four bit lines in each group. That is, bit line pairs in a first column are connected to a first sense amplifier SA1n-1 of a (n-1)th sense amplifier group SAGn-1 and a first sense amplifier SA1n+1 of a (n+1)th sense amplifier group SAGn+1, and bit line pairs in a second column are connected to a first sense amplifier SA1n-2 of a (n-2)th sense amplifier group SAGn-2 and a first sense amplifier SA1n of a (n)th sense amplifier group SAGn and a first sense amplifier SA1n+2 of a (n+2)th sense amplifier group SAGn+2. By this way, a margin is increased in the gap between sense amplifiers, the layout is relieved, and the difficulty on process is reduced.
申请公布号 JPH03212890(A) 申请公布日期 1991.09.18
申请号 JP19900069925 申请日期 1990.03.22
申请人 SANSEI ELECTRON CO LTD 发明人 SOOUUIN CHIYO;DONNIRU SHIYUU;HONNSAN FUUON
分类号 G11C11/401;G11C;G11C7/06;G11C8/02;G11C11/34;H01L21/8242;H01L27/10;H01L27/108 主分类号 G11C11/401
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