| 摘要 |
PURPOSE: To accelerate a multiplication speed by re-coding a pair of bits to leave only one multiplication or partial product for the pair of the bits and reduce the partial products to a half by using a 2-bit re-coding method. CONSTITUTION: An input port 12 for a multiplicand A is connected to a multiplicand register 20 and a pre-adder 30, a multiplicand format control port 14 is connected to the pre-adder 30 and a multiplier port 16 and a multiplier format control port 18 are both connected to a re-coder 50. A multiplexer array 70 receives the output of the multiplicand register 20, a pre-adder register 40 and a re-coded multiplier register 60 and the output is the partial product to be sent to an adder array 80. Then, the re-coder 50 re-codes the two or more bit groups of a multiplier and reduces the number of the partial products to the half. Thus, a binary multiplier provided with an accelerated speed is obtained. |
