发明名称 DELAY CIRCUIT
摘要 PURPOSE:To independently vary the rise and the fall, to adjust the timing with high accuracy, to facilitate the timing adjustment of an apparatus, and to shorten the adjustment time by inserting an integration circuit between a first comparator and a second comparator, and varying the delay time. CONSTITUTION:Between an output of a first comparator 1 having an open emitter or open collector output, and an affirmative or negative input of a second comparator 2, a CR integration circuit constituted of capacitors C1-Cn and a resistor 4 is arranged. Also, the circuit is constituted so that its capacitors C1-Cn are connected in series to switches Sw1-Swn, and also, many pieces thereof are connected in parallel, a prescribed DC comparison voltage is applied to the other input terminal of a second comparator 2, the capacitance is varied by turning-on/off of the switches Sw1-Swn and the delay time is varied. In such a way, the circuit in which each independent selectivity of a delay to a rise and a fall of a pulse signal waveform is satisfactory, a control voltage is low, and which can be converted to a monolithic IC with the maximum variable delay time set arbitrarily can be realized.
申请公布号 JPH03211913(A) 申请公布日期 1991.09.17
申请号 JP19900006159 申请日期 1990.01.17
申请人 HITACHI LTD 发明人 SAITO TAKASHI
分类号 H03K5/13 主分类号 H03K5/13
代理机构 代理人
主权项
地址