ERASABLE NON-VOLATILE STORAGE CELL, ARRAY CONNECTION SWITCHING ELEMENT OF PROGRAMMABLE LOGICALE DEVICE, AND PROGRAMMABLE LOGICAL DEVICE

摘要

PURPOSE: To shorten the switching time of a programmable logical unit by providing floating gate transistors, a read transistor and a write transistor in an EEPROM cell and preventing the occurrence of an undesired capacitive load. CONSTITUTION: Only the half of the floating gate transistors 66 and 68 is connected to a product output signal line 62. That is because only either selection transistors 74 or 76 are turned on for respective columns. Since 74 and 76 do not need to deal with programming high voltage, design can be executed by using the shortest channel length element. The capacitive loads of 74 and 76 are considerably smaller than the capacitive loads of 66 and 68. That makes the capacitive load of the product output signal line 62 to be a minimum. Since signals ROW and ROWB are not driven to super voltage, a CMOS circuit can be used for driving both signals. The voltage amplitude improves a signal margin and accelerates switching time.