Multiplier circuit for digitally coded valves - provides outputs by stages coupled to shift resistor unit

摘要

A multiplier circuit for digitally coiled numbers has inputs (A3,B3) received by shift register stages (AB) coupled to a matrix multiplier circuit (1). The circuit connects to a pair of 5 bit adder circuits (2,3), with carry propagation handled by adder stages (4). Outputss of the adder circuits connect to a shift register (5). Control of the registers is provided by a circuit that is based around a pulsed counter unit. ADVANTAGE - Uses counter control for improved performance.