| 摘要 |
In an anti-ESD protective structure, especially designed for pins destined to reach below ground and/or above supply voltages, includes a pair of Zener diodes or lateral NPN structures with a resistive connection between base and emitter, connected in opposition among each other between the pin to be protected and a grounded substrate of the integrated circuit. An amplifying effect on the leakage current which is drawn/injected through the pin by the protective structure caused by the triggering of an intrinsic parasitic transistor is effectively eliminated by connecting a biasing element, such as a forward biased junction, between the node of interconnection between the two Zener orlateral NPN structures and a node of the integrated circuit biased with a voltage sufficiently high as to ensure, under any condition, a reverse biasing of the base-emitter junction of the parasitic transistor. <IMAGE> |
