| 摘要 |
<p>An operation processing unit for processing a program that includes a function instruction, a byte logic operation instruction and a bit logic operation instruction. This unit has a control processor (1) for controlling the whole arithmetic unit, a ladder instruction memory (11) for storing a program, a processor (13) for instructing function, a processor (14) for instructing byte logic operation, and a processor (15) for instructing bit logic operation. These processors (13, 14, 15) process the programs in parallel, and the processings are arbitrated by an arbitration circuit (12).</p> |
