Supervision of microprocessors.

摘要

A microprocessor arrangement includes a microprocessor (10) that executes a program which includes a plurality of watchdog instructions (WDI1 to WDI4) which are located in respective different portions of the program and all of which should be executed during execution of the program. An address bus (14) receives addresses generated during execution of the program. An address decoder (16) is responsive to receipt of a watchdog instruction from the address bus (14) to activate one of a plurality of output lines (L1 to L4) thereof. The watchdog instructions are different from one another whereby, if the microprocessor (10) is operating correctly, the output lines (L1 to L4) will be activated in a predetermined sequence. A watchdog circuit (22) is responsive to the output lines (L1 to L4) being activated in other than the above-mentioned predetermined sequence to reset the microprocessor (10) via a reset input (RS). <IMAGE>