| 摘要 |
PURPOSE:To output clock signals without any hit even if any of input signals is lost by reducing the amplitude of each clock signal to half in order, and deriving the clock signals according to the zero-cross point of the signal obtained by adding those clock signals. CONSTITUTION:When the sine waves of a in-use system and a 1st stand-by system are inputted, clock signal generating circuits 1-3 generate rectangular wave clock signals CK0-CK2 with amplitudes A, 1/2A, and 1/4A at timing corresponding to the zero-cross points of the respective sine waves. Those are added by a wide-band voltage adding circuit 4 to generate a superposed signal S1. Then a zero-cross voltage comparing circuit 5 detects the zero-cross point of the superposition signal S1 to generate the clock signal CK3, which is supplied to respective parts of a device. Therefore, priority can be given on the signal having the maximum amplitude value. Consequently, only one clock signal can be derived without making any hit while not using any special switching means. |
