| 摘要 |
PURPOSE:To reduce the power consumption without increasing the busy rate by specifying the number of unit amplifying circuits of a sense amplifier which practically have the n-bit storage capacity and are simultaneously activated in the normal access cycle and the refresh cycle. CONSTITUTION:A device fundamentally has the n-bit storage capacity, and row addresses R0 to Rsq. rt. n-1 whose number ra is >=sq. rt. n, namely, 4096, and one word line, namely, 1/ra word lines corresponding to the practically designated row address Ri are set to the selected state in the alternative way, and one pair of complementary bit lines corresponding to a designated column address Cj are set to the selected state in the alternative way. Consequently, a number sa of unit amplifying circuits of the sense amplifier which are activated in each access cycle is <=sq. rt. n, namely, 4096, and it is a half in comparison with a normal dynamic RAM. Thus, the busy rate is suppressed and the power consumption is reduced. |
