| 摘要 |
PURPOSE:To obtain a semiconductor device of high integration degree, by constituting an element isolation region formed on a semiconductor substrate surface by using a conducting layer which covers the isolation region and stretches as fast as the element region, and connecting said layer with a constant voltage source. CONSTITUTION:Between adjacent element regions 6, a region exists where element isolation regions are smaller than those of the other parts and closely neighbored to each other. On said region, a second polycrystalline Si electrode 8 is arranged, which is connected with a constant voltage source and stretches on the region 6. Even in the case of a parasitic MOS transistor whose element isolation region width is short, e.g. 0.6mum, electric conduction is not generated and the breakdown strength between elements is not deteriorated even when a supply voltage happens to change larger than or equal to 20%, because the transistor has a threshold value of about 5V. Hence the element isolation region width can be reduced, and the integration degree of an element can be increased. |
