| 摘要 |
PURPOSE:To obtain a DRAM whose cell size is small in spite of large capacitor area, by burying the capacitor of a memory cell in a substrate under a selection transistor. CONSTITUTION:One out of the source and drain 26 of a selection transistor Tr 2 is connected with the capacitor 4 of a memory cell, and the other one is connected with a bit line 8. The gate 32 of the Tr 2 is connected with a word line. The other electrode 22 of the capacitor 4 is connected with a GND line. Concerning to each memory cell, a cavity 16 is formed in an Si substrate 14, and the inner wall of the cavity 16 is insulated with an Si oxide film 18. In the capacitor 4, a dielectric film 24 is formed between a charge storing node 20 and a cell plate 22, and the node 20 is connected with the source and drain 26 of the Tr 2. The Tr2 is formed above the cavity 16. In this manner, the capacitor 4 is buried in the substrate under the Tr 2. |
