Emitter coupled logic circuit.

摘要

An emitter coupled logic circuit (25) for supplying a load with first and second logic levels comprising a pull-up circuit (29) including a bipolar transistor (29) connected to supply a first voltage level to said load in response to a first signal from said ECL logic stage (25); and a pull-down circuit connected to supply a second voltage level to said load, comprising a junction field effect transistor (30) connecting said load to a second voltage level in response to a second signal from said ECL logic stage (25), said junction field effect transistor (30) having a back gate (32) connected to a potential which increases current flow from said load through said junction field effect transistor (30) in response to said second signal. <IMAGE>