PLL circuit for producing a clock signal

摘要

A PLL circuit for use in a disk playing apparatus is constructed such that an oscillation output of a VCO is frequency divided at a frequency dividing ratio corresponding to a designated linear velocity in the disk playing apparatus. The frequency divided signal is derived as a reproduction clock signal and a gain of a variable gain amplifier which amplifies a phase error signal and uses the amplified signal as a control voltage of the VCO is changed in accordance with the designated linear velocity, so that a stable loop characteristic is always obtained.