| 摘要 |
PURPOSE:To add synchronizing information such as frame synchronizing signals, etc., to a virtual group signal by adding the synchronizing information, which are used for a signal processing in a device, to the virtual group signal by inverting the prescribed bit of a reserve bit part in the virtual group signal. CONSTITUTION:For a fixed reserve byte, the bit is inverted by passing the fixed reserve byte through the inverter circuit of a reserve byte code part 11, converted to the frame synchronizing signal and sent to a switch part 2. The virtual group signal cross-connected at this switch part 2 is sent to an output interface part 3 and frame synchronization is obtained by the frame synchronizing signal inserted to a reserve byte position in this virtual group signal. Further, for this frame synchronizing signal, the bit is inverted again by passing the signal through the inverter circuit of a reserve byte decoder part 31, and returned to the original reserve bit. |
