| 摘要 |
PURPOSE: To enhance various properties of a device and performance of a very large scale integration(VLSI) interlayer dielectric by forming a dielectric layer onto a conductive layer and then forming a glass layer onto the dielectric layer before annealing the glass layer in an environment. CONSTITUTION: A metal layer 202 is formed, at first, on a semiconductor body 201 and an opening is made between patterned parts on the metal layer 202. An oxide layer 203 is then formed by CVD and a spin-on glass(SOG) layer 204 of about 3000-8000Åis formed thereon. Subsequently, the SOG layer 204 is annealed at about 350-450 deg.C and a semiconductor device is placed in a flow of nitrogen bubbled through an organic silicon compound heated at about 50 deg.C and cooled down to the room temperature from the annealing temperature. A thicker SOG layer can thereby be formed without causing a large crack over a wide range and the performance of semiconductor device is enhanced while increasing the yield.
|
