发明名称
摘要 A circuit arrangement is described for automatically monitoring several analog electric signals and for maintaining predetermined ranges of tolerances by successive comparison with reference values. Error alarm signals are produced and stored, dependent upon the comparison and timed (synchronized) simultaneously with the connection of the respective signals to be monitored to a comparator (20). Access is provided to a reference value storage (30) from which reference signals assigned to each single signal and ranges of tolerances defining reference values are timed and led to the comparator (20). The respective outlet (output) signal of the comparator (20) for producing similar error alarm signals to be stored is logically linked with an evaluating signals (ZB 0) indicating which of the two reference values lies at any time on the comparator (20).
申请公布号 JPH0357660(B2) 申请公布日期 1991.09.02
申请号 JP19860277798 申请日期 1986.11.21
申请人 JIIMENZU NITSUKUSUDORUFU INFUOMEESHONZUSHISUTEMU AG 发明人 UORUFUGANGU ETSUZAA;PEETAA YUNGU
分类号 H04B17/00;G01R19/165 主分类号 H04B17/00
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