| 摘要 |
PURPOSE:To match frame phases of respective devices connected in a multistage by outputting a synchronous frame pulse within a fixed range from the changing point of an inputted reference frame pulse and absorbing the jitter generated between the changing point of the reference frame pulse and the rising or falling point of a reference clock pulse. CONSTITUTION:Even when a reference frame pulse FP0 is inserted after or before the rise of a clock signal CK, a load pulse EG is sent 0.5-bit width of the clock pulse CK, and a frame pulse FP1 is sent within the fixed range from the change point of the reference input frame pulse FP0. Even when the reference frame pulse FP0 has jitter (deviation) to the rise of the clock signal CK, the frame pulse FP1 is stably sent. Thus, frame phases of respective devices using transmission lines connected in multistage are matched with each other. |
