Frame synchronization circuit.

摘要

In a frame synchronization circuit, a serial data signal, which includes a frame synchronization code constituted by an M number of bits in one frame, is converted by a serial/parallel converting circuit (10) to a parallel data signal of a 2M-1 number of bits. An M number of pattern detectors (#1 to #M) of a first synchronization detecting circuit (20) detect the code pattern of the first block of the frame synchronization code from the parallel data signal. A selection signal generating circuit (30) holds outputs of the pattern detectors (#1 to #M), and outputs them as a selection signal designating the bit position allotted to the pattern detector which detects the synchronization code pattern. An output of the serial/parallel converting circuit (10) is delayed by a time required for the above-mentioned processing, and supplied to a selector (40), which selectively outputs an M-bit data signal corresponding to the bit position designated by the selection signal. <IMAGE>