| 摘要 |
<p>Delay analysis in logic simulation is enhanced by providing, in a simulation model of a logic circuit, a timing delay tag on each circuit path connecting the output (30;10) of a first (BLK1;BLK4) with the input (A0,D01) of the second circuit element (BLK4;BLK3). Each circuit leg is given a delay value and a clock phase tag providing information about how the delay value is clocked. The clock phase tags (T0,...,T3) correspond to respective phases of a multi-phase circuit clock and relate the delay values to particular clock phases. The phase tag also indicates whether the signal on the data path is triggered by the rising (R) or falling edge of the specified clock phase. At circuit nodes, clock phase tags are concatenated. Thus, if a clocked circuit element responds to an input signal which is a composite of several upstream output signals, the concatenated clock phase tags and delay values can be analyzed to determine if a timing adjustment is required. The information further supports the automatic adjustment of delay value, if needed. <IMAGE></p> |
