Output buffer circuit with output voltage sensing for reducing switching induced noise.

摘要

An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor (N1) element with the current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element (N3). A first output voltage sensing switching circuit (P4) is coupled in series between the control terminal leads of the secondary (N1) and primary pulldown (N1) transistor elements. The secondary pulldown transistor (N1) element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer first. A relatively small discharge current is therefore initiated from the output before turn on of the relatively large discharge current of the primary pulldown transistor element (N3). The first output voltage sensing switching circuit delays turn on of the primary pulldown transistor (N3) element until a threshold voltage below high potential is reached at the output. As result ground bounce and undershoot are each divided into two spikes and the ground rise in potential is constrained to approximately one half that of conventional ground bounce levels. A secondary pullup transistor element with associated noise reduction components can similarly be used on the supply side to reduce VCC droop and overshoot including a second output voltage sensing switching circuit. <IMAGE>