发明名称 |
Soft error immune memory |
摘要 |
An alpha radiation immune integrated circuit memory cell has a pair of secondary transistors connected to cross-couple the primary transistors to form a flow, secondary storage node. The secondary transistors are biased to a standby current that, in combination with the parasitic capacitances in the new cell, establishes a time constant sufficient to maintain the state of the secondary nodes during an alpha hit on the primary nodes, so that alpha immunity is achieved without added capacitance. A write boost circuit increases the current in the secondary transistors during a write operation. A memory array is formed of rows of such cells with all of the secondary emitters of each row coupled to a common emitter standby current source. The individual row emitter standby current sources are coupled together through a balanced resistor network so that the excess secondary emitter current generated during a write operation in a selected row is distributed across the non-selected rows, thereby maintaining the total secondary emitter current constant for the array.
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申请公布号 |
US5043939(A) |
申请公布日期 |
1991.08.27 |
申请号 |
US19890366737 |
申请日期 |
1989.06.15 |
申请人 |
BIPOLAR INTEGRATED TECHNOLOGY, INC. |
发明人 |
SLAMOWITZ, MARK N.;LEFFERTS, ROBERT B. |
分类号 |
G11C5/00;G11C11/411;G11C11/415;G11C11/416 |
主分类号 |
G11C5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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