| 摘要 |
A pipe-lined data processor system comprising a plurality of processors interconnected in the form of a pipe line, a plurality of memory apparatus connected to each of the processors through output data buses for supplying data to the processors or storing data from the processors, and a control board connected to the memory apparatus through input data buses for managing the operation sequences of the processors and the memory apparatus, wherein the plurality of memory apparatus comprise each a main memory for storing the data to be processed as predetermined by the processors or the data having been processed as predetermined by the processors, a buffer memory for temporarily storing the data, first control means for controlling the timing of input/output of the data between the main memory and the buffer memory, and second control means for controlling the timing of input/output of the data between the buffer memory and the input/output buses.
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