| 摘要 |
PURPOSE:To improve the application efficiency of hardware by using a mode signal which prescribes the number of elements to which simultaneous accesses are possible to correct the difference between the address information on the final element of the 1st data and that on the head element of the 2nd data. CONSTITUTION:An adder circuit 1 calculates the bank address of the final element of data and supplies it to a register 2. A subtractor circuit 3 uses a mode signal which prescribes the number of elements to which the simultaneous accesses are possible to calculate the difference between the bank addresses of the final and head elements of data given from the register 2 and supplies the obtained difference to a gate circuit 4. A shift circuit 5 shifts the difference of the bank addresses masked by the circuit 4 and supplies it to a subtractor 8. The circuit 8 obtains the difference between the difference of the shifted bank addresses and the contents of a register 6 and supple is it to an inverting circuit 9. The register 6 receives selectively the information on the memory bank cycle time and the output of a subtractor circuit 7. Then an access start valid signal is led out of the circuit 9. |
