CACHE ACCESS ON THE BASIS OF TRANSLATION LOOK AHEAD

摘要

PURPOSE: To increase an address accessing speed by preparing a cache access system which can avoid the synonym problem designated by a logical address while reducing both address generation and cache access machine cycles. CONSTITUTION: A cache memory access system 5 retrieves the data that are used by an arithmetic and logic unit ALU 500 in a machine cycle set after an instruction is decoded as long as the requested data are stored in a cache memory 410 of a computer after the decoding of the instruction. The results of a presumed real address generation means PRAGM 200 and a virtual address generation means VAGM 300 are inputted to a presumed real address register PRAR 30 in an instruction decoding machine cycle. When a latent virtual address is coincident with the virtual address of a virtual address register VAR 40, a transformation lookaside buffer TLB 420 selects a real address corresponding to the coincident latent virtual address.