发明名称 METHOD OF INHIBITING DRAIN DISTURBANCE OF EEPROM ARRAY AND EEPROM CELL
摘要 <p>PURPOSE: To suppress an operation that is similar to erasure leading to a drain disturbance by selectively making a gate oxide thick on a channel region closest to a drain and maintaining the gate oxide film closest to a source region and located directly above the source region as thin as possible. CONSTITUTION: Each of a read only memory cell 14 that can be electrically erased and written includes a source region and a drain region that are formed in a silicon substrate a floating gate 11 that is insulated from a channel is arranged at the upper part of the channel being formed between the regions, and a control gate electrode 13 is arranged at the upper part of the floating gate and is insulated from the floating gate. Then, to promote thermal oxidation generated in it, the lattice structure of the channel part close to the drain region is damaged intentionally. Since a part close to the drain of the channel is damaged intentionally, the thickness of a tunnel oxide that covers the region becomes further larger, as compared with the remaining part of the channel, thus suppressing an operation that is similar to erasure, leading to drain disturbance.</p>
申请公布号 JPH03195059(A) 申请公布日期 1991.08.26
申请号 JP19900313019 申请日期 1990.11.20
申请人 INTEL CORP 发明人 JIIICHIEN JIEI TSUEN
分类号 G11C17/00;G11C16/04;H01L21/28;H01L21/316;H01L21/8247;H01L27/115;H01L29/423;H01L29/49;H01L29/788;H01L29/792 主分类号 G11C17/00
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