| 摘要 |
PURPOSE:To reduce leak current to a substrate by a parasitic transistor, a reverse flow current caused by reverse operation of a transistor, etc., and to improve an operation speed by making an impurity concentration of a base layer of a vertical transistor of a memory cell region higher than that of a base layer of a vertical transistor in a peripheral circuit region. CONSTITUTION:An impurity concentration of a base layer 103B of a first vertical n-p-n transistor of a memory cell part (b) is made higher than that of a base layer 104 of a second vertical npn transistor of a peripheral circuit part (a). A diffusion constant of first impurities used for formation of a first buried collector layer 2B of the first vertical transistor is made larger than that of second impurities used for formation of a buried collector layer 2A of the second vertical n-p-n transistor. The base layer 103B of the first vertical n-p-n transistor and a collector region 3 of the first vertical n-p-n transistor are formed to a base region and a collector region, respectively. An emitter region 102B of a lateral p-n-p transistor is provided in contact with the first buried collector layer 2B. |
