发明名称 PHASE LOCK LOOP
摘要 PURPOSE: To eliminate the necessity of external parts and to display performance higher than a reference phase lock loop(PLL) by providing a PLL with both analog and digital functions in a composite digital and analog circuit provided with an analog PLL. CONSTITUTION: A 2nd phase detection part 20 detects a phase difference between a 19kHz feedback signal obtained from an analog PLL 28 and a 19kHz pilot signal included in an FM synthetic signal. The analog PLL 28 acts as a smoothing filter for a 19kHz signal D and is used for the generation of a 38kHz sine wave to be used for a signal route of an FM decoder. The signal D is turned to accurate frequency by the digital part of the analog/digital PLL and its phase noise is reduced by the analog part of the PLL. Thereby high performance capable of minimizing a phase error and attaining the accuracy of the digital PLL having no phase noise can be obtained.
申请公布号 JPH03192821(A) 申请公布日期 1991.08.22
申请号 JP19900215684 申请日期 1990.08.14
申请人 DERUKO ELECTRON CORP 发明人 RICHIYAADO ARUBAATO KENEDEII;GUREGORII JIYON MANRABU;JIEFURII JIYOSEFU MAARAA
分类号 H03L7/087;H03D1/22 主分类号 H03L7/087
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