| 摘要 |
PURPOSE:To execute filtering by an arithmetic circuit, which hardware quantity is approximately 1/p to the conventional quantity, by executing cascade connection upon a (q) pieces of sum of products computing elements to execute constant multiplication and the integration of multiplied results respectively (p) times in respect to the (p) pieces of picture element values. CONSTITUTION:A two-dimensional FIR digital filter multiplies coefficients to the (p) pieces of lateral picture elements and the (q) pieces of longitudinal picture elements, totally, to the [(p)X(q)] pieces of the respective picture elements and executes the arithmetic of the sum of products to add those multiplied results. In such a case, the sum of products arithmetic to the (p) pieces of the lateral picture elements is executed while repeating multiplication and addition by a sum of products arithmetic circuit 1a composed of a multiplier 2a, adder 3a and delay circuit 5a surrounded by a broken line. The cascade connection is executed upon the (q) pieces of the sum of products arithmetic circuits and the sum of products arithmetic is executed upon the totally [(p)X(q)] pieces the picture elements. Thus, since the numbers of the multipliers, adders and delay circuits are made 1/p in comparison with the conventional circuit, the hardware quantity can be reduced. |
