| 摘要 |
PURPOSE:To save the number of external terminals for a control signal input by providing a counter circuit inside of a PLL circuit, and using output signals of a counter circuit and a data latch circuit to transfer the dta of the data latch circuit to a programmable divider. CONSTITUTION:A counter circuit 13 counts the number of clocks inputted from a clock input terminal 3. When the number reaches a prescribed number, a latch signal is outputted to a latch selection circuit 12. The latch selection circuit 12 uses the latch signal from the counter circuit 13 and the signal from the data latch circuit 10 to transfer a data stored in the data latch circuit 10 to a programmable divider 7 or 8. Moreover, when a control signal to transfer the data is outputted from the latch selection circuit 12 to the selection circuit 11, since the built-in counter circuit 13 is reset, the number of external control signal input terminals is saved. |
