| 摘要 |
A reduced instruction set type microprocessor which reduces loss of central processing unit (CPU) time. A circuit is provided to identify and keep track of whether an arithmetic instruction requires operands contained in internal registers or in main memory. First and second execution stage circuits are provided for executing the first and second instruction executing functions, respectively. The first execution stage circuit performs address calculation if the instruction involves main memory. The second execution stage circuit selects the appropriate operands and performs the arithmetic operation.
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