| 摘要 |
A system for convolutional interleaving of data bits in accordance with preselected convolutional interleaving parameters employs random access memory (RAM) and control thereof is provided by WRITE and READ column and row signals, which are generated responsively to the interleaving parameters and permit realization of the system with memory requirements slightly more than shift register interleavers but substantially less than hetertofore known RAM interleaver implementations. In one system embodiment, the system output data bits involve both RAM output and the incoming data bit. In another system embodiment, pseudo random convolutional interleaving is attained, again responsively to the preselected convolutional interleaving parameters. In either system, the parameters may be changed as desired to accommodate performance need.
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