| 摘要 |
PURPOSE:To facilitate the higher integration of a memory cell by a method wherein a drain part, an active layer and a gate part, a source part and a capacitor part of a MOS transistor are laminated in the vertical direction on a semiconductor substrate. CONSTITUTION:An N type layer 2 to be a drain part in the impurity concentration exceeding 1X10<18>/cm<2> is formed on a P type Si substrate 1 and then a P type layer 3 in the impurity concentration not exceeding 1X10<18>/cm<2> is formed on the layer 2. This layer 3 is etched away to be formed in a post shape and then insulating films 4 are formed on the sidewalls of the layer 3 and the surface of the layer 2. Later, polycides are formed into gate electrodes 5 to be formed after a specific pattern. Next, the layer 3 is exposed to form an N type layer 7 to be a source part in the impurity concentration exceeding 1X10<18>/cm<2>. Next, an N type Si layer 8 to be an electrode is formed on the N type layer 7 and then an oxide film 9 is formed after another pattern on the surface of the layer 8. Furthermore, another electrode 10 is formed on the film 9 to complete a memory cell. |
