| 摘要 |
PURPOSE:To simplify a change procedure such as the order of processing connection by adding the input/output of a frame pulse and a clock signal in addition to the input/output of data. CONSTITUTION:Respective LSI 10 and 11 receive input data D1 and D2 to be processed, receive frame pulses FP(1) and FP(2) showing the leading timing of the respective input data D1 and D2 to a clock signal CLK, generate frame pulses FP(2) and FP(3) showing the leading timing of output data D2 and D3 to a control signal for data processing in control parts 20 and 21 and control the processing operations of processing parts 30 and 31. Thus, in the case of a processing with the cascade connection of the LSI, the control signal is not newly required and even when the order of the processing connection is changed, it is not necessary to change the LSI itself. |
