| 摘要 |
PURPOSE:To prevent the dispersion of characteristics due to variations in the width of an offset region by forming a gate electrode layer with a uniform width inward by a specified width from an end face of a resist pattern by isotropic etching, and an offset region with a uniform width in a polysilicon active layer below an overhang by ion implantation into the polysilicon active layer. CONSTITUTION:A substrate 1 having a bulk transistor 1A covered with an insulating film 1B is overlaid with a polysilicon active layer 2 and an insulating film 3, which is in turn topped with a gate electrode layer 4 by isotropic etching with the mask of a resist pattern 5. The overhang width 6 of the resist pattern 5 over the gate electrode layer 4 serves as an offset, while a source 9A, a drain 9B, and an offset region 6' adjacent to both and to a channel 8 are formed by implantation of impurity ions 7 into the polysilicon active layer 2. This process can prevent the dispersion of characteristics due to variations in the width of an offset region. |
