| 摘要 |
PURPOSE:To enable plural frequency dividers to operate in synchronizing with one another at all times by generating a forcible synchronizing signal, which is the least common multiple of frequency division ratios of the frequency dividers, by a divider. CONSTITUTION:The divider 5 performs frequency division by the least common multiple of a 1/n frequency divider 1 and a 1/m frequency divider 3, i.e., 1/6 frequency division. The leading edge of the forcible synchronizing signal waveform which is generated at time t2 is therefore inputted forcibly to the input terminal In of the 1/m frequency divider 3 through an OR circuit 15, and the frequency division output of the 1/m frequency divider 3 is synchronized forcibly with the 1/n frequency divider 1 at time t2, so the output rises at the same timing. Thus, the 1/m frequency divider 3 is synchronized forcibly with the frequency division output of the 1/n frequency divider 1 at specific timing (after waveform outputs whose number corresponds to the least common multiple of the frequency division ratios are outputted). Consequently, the 1/n frequency divider 1 and 1/m frequency divider 3 can be synchronized with each other at all times. |
