| 摘要 |
<p>PURPOSE:To prevent an error due to an outrun from being generated by setting a specific write-side reset signal and a read-side reset signal, which are free from the outrun, synchronously. CONSTITUTION:When the read-side reset signal RR is less than F/2 from its frame cycle F according to the write-side reset signal WR, the shift quantity of a variable stage number shift register 2 is controlled with F/2+x calculated by a 1st arithmetic part 5. Further, when F/2 is exceeded, the shift quantity is controlled with x-F/2 calculated by a 2nd arithmetic part 6. Thus, an input- side counter is operated from the center time of the frame cycle of the read-side reset signal RR in either case. Consequently, the error caused by the outrun depending upon the timing between write operation and read operation is eliminated.</p> |
