发明名称 |
Logic circuit for use in D/A converter having ECL-type gate structure. |
摘要 |
<p>A logic circuit outputs state signals of seven different kinds, on the basis of first, second and third digital signals. A first composite gate circuit (11) outputs a logical OR among the first to third digital signals as a first state signal. A first gate circuit (14) outputs a logical OR between the second and third digital signals as a second state signal. A second composite gate circuit (15) is supplied with a logical AND between the first and second digital signals, and outputs a logical OR between the supplied logical AND and the third digital signal as a third state signal. A third composite gate circuit (18) is supplied with a logical OR between the first and second digital signals, and outputs a logical AND between the supplied logical OR and the third digital signal as a fifth state signal. A second gate circuit (21) outputs a logical AND between the second and third digital signals as a sixth state signal. A fourth composite gate circuit (22) is supplied with a logical AND between the first and second digital signals, and outputs a logical AND between the supplied logical AND and the third digital signal as a seventh state signal. The third digital signal is output as a fourth state signal without being processed. Each of the above circuits has an emitter coupled logic structure. <IMAGE></p> |
申请公布号 |
EP0440866(A1) |
申请公布日期 |
1991.08.14 |
申请号 |
EP19900102579 |
申请日期 |
1990.02.09 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SUGIYAMA, HISASHI, C/O INTELLECTUAL PROPERTIES DIV;NAKAMURA, MICHINORI, C/O INTELLECTUAL PROPERTIES D;SUGIMOTO, YASUHIRO, C/O INTELLECTUAL PROPERTIES D |
分类号 |
H03M7/00;H03K19/086;H03M7/14;H03M7/16 |
主分类号 |
H03M7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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