发明名称 FAIL-SAFE MODULAR MEMORY
摘要 A modular fail-safe memory and an address generation mechanism that provides load balancing when the memory is shared by a number of processors (320). A plurality of memory modules (10a-m) are used for the memory with no specific limit on the number of memory modules, and a checksum block is used to back-up corresponding blocks in the other memory modules. The checksum blocks are distributed across the memory modules, and an address generation mechanism (Fig. 2 and 3) determines the checksum location for a specific memory block. This address generation mechanism ensures that checksum blocks are equally divided between the memory modules (10a-m) so that there is no memory bottleneck, is easy to implement in hardware, and is extended to provide similar properties when a module failure occurs.
申请公布号 EP0371243(A3) 申请公布日期 1991.08.14
申请号 EP19890119306 申请日期 1989.10.18
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 IYER, BALAKRISHNA RAGHAVENDRA;DIAS, DANIEL MANUEL;DISHON, YITZHAK
分类号 G06F12/16;G06F3/06;G06F11/10;G11C29/00;(IPC1-7):G06F11/08 主分类号 G06F12/16
代理机构 代理人
主权项
地址