发明名称 TEST CIRCUIT
摘要 PURPOSE:To increase input pins by giving a three state buffer to an output buffer and providing a non-coincidence (or coincidence) circuit in which the input signal line of the output buffer and a signal line connected to an output terminal are set to be inputs, and a latch in which the output of the non- coincidence (coincidence) circuit is set to be the input. CONSTITUTION:The three state buffer 101 is connected to a connection point S11 and the buffer 101 is connected in a connection point 105 as the input of the non-coincidence circuit 102. A connection point 104 is inputted to the non- coincidence circuit 102 and the output signal of the non-coincidence circuit 102 is inputted to a latch 103. Furthermore, the output of the latch 103 is outputted to a connection point S13, and an internal circuit which operates by a trigger signal is connected to the connection point S13, whereby signals K11 and K11 whose phases are opposite are connected to the three state buffer 101 and the latch 103. Thus, the terminal which is usually used as the output can be used as an input terminal by a control signal given to the output buffer.
申请公布号 JPH03186938(A) 申请公布日期 1991.08.14
申请号 JP19890326890 申请日期 1989.12.15
申请人 NEC CORP 发明人 KISHIBE KOJI;SAKURAI YOSHIKAZU
分类号 G01R31/28;G06F11/22;H01L21/66 主分类号 G01R31/28
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