Phase lock circuit and resulting frequency multiplier.

摘要

The phase locked circuit (10) comprises a phase comparator (11) receiving an input signal (CL) and a feedback signal (FB). The feedback signal is produced by a delay circuit (13) imposing a variable phase delay on the input signal. The delay is controlled by the output signal of the phase comparator. The delay circuit is made up from an integer number (N) of delay elements (130-137) mounted in series, producing respective equal delays dividing the time interval between two predetermined recurrent fronts of the input signal.