| 摘要 |
PURPOSE:To invalidate only data sent and arrived when erroneous data was sent and arrived, and to minimize the fall of performance by determining whether an effective bit is to be made effective or not according to the calculated result of a redundant information calculation circuit. CONSTITUTION:A parity control circuit 212 calculates a syndrome form the sent data and parity information sent from a parity latch 213 through an internal parity bus 232, and decides whether the sent data is correct or not. When the sent data is decided to be ineffective, an effective bit control circuit 223 does not make one of the corresponding bits of a cache memory active. Thus, since the erroneous data need not be stored when the erroneous data is sent and arrives because of a noise, etc., during the transfer of an instruction or the data, or when the contents of a memory is broken because of the soft error of the memory, the fall of the performance is made small. |
