发明名称 Method and apparatus for handling nested interrupts.
摘要 <p>A microprocessor (10) including unprime registers (20) for use during normal operation, prime registers (22) for use during interrupts, a normal register set (16) for use during normal operation and conventional interrupt operations, an alternate register set (18) for use during fast interrupt operations, and a memory stack (50). Three status bits (26,28,30) are used to indicate that one or more fast interrupts have been initiated but not completed, that a fast interrupt is occurring but there are no other fast interrupts being processed, and that the CPU (14) is currently processing a fast interrupt. These status bits (26,28,30) indicate if there is a recursion jeopardy and are used to control the flow of information between the normal (18) and alternate register(18) sets and the memory stack (50) in order to prevent recursion. &lt;IMAGE&gt; &lt;IMAGE&gt;</p>
申请公布号 EP0441054(A1) 申请公布日期 1991.08.14
申请号 EP19900314038 申请日期 1990.12.20
申请人 MOTOROLA, INC. 发明人 COHEN, ROBERT B.;GARNER, ROBERT E.
分类号 G06F9/30;G06F9/46;G06F9/48 主分类号 G06F9/30
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