| 摘要 |
PURPOSE:To improve the correction effect of a bit error correction circuit up to a level almost close to a theoretical value by synchronizing a counter with a correct frame synchronizing pulse and using an output pulse of the counter as a frame synchronizing pulse thereafter. CONSTITUTION:Since a delay circuit 3 delays an SQ signal 30 by a time corresponding nearly to a preamble 11, an output of the circuit 3 is logical H when a first frame synchronization pulse 20 is outputted and the pulse 20 generated immediately after an FF 51 is set passes through a gate 7 to set an FF 52. When the FF 52 is set, the pulse 20 is blocked by a gate 81 and an output pulse 22 of the counter 4 pass through gates 82, 83 and the pulse is used as a correct frame synchronizing pulse 23. Then the FF 51 is set when the count of the counter 4 is (n-1) and reset when the count of the counter 4 is logical 1 but no effect is given to the FF 52. The pulse at a point of time t4 in waveform diagram is a correct frame synchronization pulse and the output pulse 22 of the counter 4 is used as the correct frame synchronizing pulse. |
