| 摘要 |
<p>PURPOSE:To efficiently utilize a data buffer by allowing a storage device to execute the 2nd operation when an instruction execution part executes an instruction at the time of setting up the 2nd value in a storage device control information holding means as storage device control information. CONSTITUTION:When the TG bit 7 and T bit 9 of a debugging control register are set up to '0', the data buffer 202 operates as a normal data cache. When the DB bit 24 of a processor status word(PSW) is '1' and the TG bit 7 and T bit 9 of the debugging control register are set up to '1', the data buffer operates as a trace memory and stores a program counter value calculated by a PC calculating part for an instruction executed by an operation part as a trace information. Consequently, the data buffer 22 can be used also as the trace memory in addition to the cash memory and the data buffer 202 can be efficiently utilized.</p> |
