| 摘要 |
A time division speech path apparatus includes a frame synchronization detector, a pointer detector, a pointer inserting circuit, an address converter, a selector, and a demultiplexer. Pointers are set on highways so that a relationship between the time slots on the highways and read addresses for the speech path control memory is determined on the basis of the frame phases and pointer values of the respective highways. Data which are read out from the speech path control memory in accordance with addresses based on this relationship are written in the speech path memory as read addresses therefor. In addition, sequential addresses generated by the counter operated in accordance with the specific read phase of the system are provided to the speech path memory as read addresses therefor.
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