| 摘要 |
PURPOSE:To compress circuit scale by comprising a frame counter of a counter which counts the prescribed number of digits (=45N) of one row corresponding to multiplicity N, and a counter which counts the number (=9) of rows per one frame connected to the counter in series. CONSTITUTION:When the content of a 10-bit counter 211 arrives at a count value [539] corresponding to the number [540(=45 digits X 12 multiplex)] of digits included in a unit row, the output signal of a decoder 212 goes to a high level. The 10-bit counter 211 is reset corresponding to the signal, also, a four-bit counter 221 goes to a count enable state, then, it is counted up. Meanwhile, the four-bit counter 221 performs a count operation corresponding to the output signal of the decoder 212 in the frame counter 210, and when the content arrives at a count value [8] corresponding to the number [9] of rows included in a unit frame, it is reset corresponding to the output signal of a decoder 222. Therefore, a conventional frame counter circuit comprised of a 13-bit counter and the 10-bit counter can be comprised of the 10-bit counter and the four-bit counter. |
